library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity SF_receive_side is
  port( 							
    clk, reset: in std_logic;
	--inputs from rcv to SF_rcv_interface
	rcv0_data, 	rcv1_data, 	rcv2_data, 	rcv3_data: in std_logic_vector(7 downto 0);
	rcv0_length,rcv1_length,rcv2_length,rcv3_length: in std_logic_vector(11 downto 0);
	rcv0_qempty,rcv1_qempty,rcv2_qempty,rcv3_qempty: in std_logic;

	--outputs to rcv from SF_rcv_interface
	rcv0_drdreq, 	rcv1_drdreq, 	rcv2_drdreq, 	rcv3_drdreq: out std_logic;
	rcv0_lrdreq, 	rcv1_lrdreq, 	rcv2_lrdreq, 	rcv3_lrdreq: out std_logic;

	--inputs from SF_table_interface to RecHandle
	--there are none

	--outputs from RecHandle to SF_table_interface
    rcv_port_number_to_xmt: out std_logic_vector(1 downto 0);
	
	

	--output port number FIFO signals 
--	pfifo_wreq:		out std_logic;  						--written by table interface
--	pfifo_full:		in std_logic; --pfifo will never be full (pfifo_full)
--	pfifo_input:	out std_logic_vector(2 downto 0); 		--written by table interface
	
	--address FIFO signals
	afifo_wreq:		out std_logic;
	afifo_empty: 	in std_logic;
	afifo_input:	out std_logic_vector(7 downto 0);
	
	--length FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
	lfifo_wreq:		out std_logic;
	lfifo_full: 	in std_logic;
	lfifo_input: 	out std_logic_vector(11 downto 0);

	--data FIFO signals inside SF_ODLFifo_xmtInterface_Xmt0to3
	dfifo_wreq:		out std_logic;
	dfifo_full: 	in std_logic;
	dfifo_input: 	out std_logic_vector(7 downto 0)



  );  
end SF_receive_side;

Architecture arch of SF_receive_side is 

------------Signals

	--outputs from rcv_interface to RecHandle
	signal rcv_port_number_from_rcv: std_logic_vector(1 downto 0);
	signal rcv_connection_ready: std_logic;
	signal rcv_data: std_logic_vector(7 downto 0);
	signal rcv_length: std_logic_vector(11 downto 0);
		
	--inputs from RecHandle to rcv_interface
	signal rcv_drdreq, rcv_lrdreq, packet_finished: std_logic;

------------Components
	component SF_rcv_interface is
	port(
		reset, clk: in std_logic;
		--inputs from Xuan
		rcv_drdreq, rcv_lrdreq, packet_finished: in std_logic;

		--inputs from RCV ports
		rcv0_data, 	rcv1_data, 	rcv2_data, 	rcv3_data: in std_logic_vector(7 downto 0);
		rcv0_length,rcv1_length,rcv2_length,rcv3_length: in std_logic_vector(11 downto 0);
		rcv0_qempty,rcv1_qempty,rcv2_qempty,rcv3_qempty: in std_logic;
		
		--outputs to Xuan
		rcv_data: out std_logic_vector(7 downto 0);
		rcv_length: out std_logic_vector(11 downto 0);
		
		port_number: out std_logic_vector(1 downto 0);
		connection_ready: out std_logic;
		
		--outputs to RCV ports
		rcv0_drdreq, 	rcv1_drdreq, 	rcv2_drdreq, 	rcv3_drdreq: out std_logic;
		rcv0_lrdreq, 	rcv1_lrdreq, 	rcv2_lrdreq, 	rcv3_lrdreq: out std_logic
	);
	end component;

	component RecHandle is
	port
	( 	
		clk: in std_logic;
		reset: in std_logic; 
		
		--3 ports out to Bryan
		Data_Read: OUT STD_LOGIC; 
		Length_Read: OUT STD_LOGIC;
		Packet_Finished: OUT STD_LOGIC;
		
		--4 ports in from Bryan
		Data: in std_logic_vector(7 downto 0); 
		Packet_Length: in std_logic_vector(11 downto 0); --include data valid
		Connection_Ready: in std_logic;
		Input_Port_Number: in std_logic_vector(1 downto 0);

		--1 port in from data FIFO
		FIFO_Full: in std_logic;  --added for monitoring the data FIFO
		
		--2 ports to data FIFO
		Data_Output: out std_logic_vector(7 downto 0);
		Data_wrreq: out std_logic;
		
		--1 port from addr fifo		
		Address_FIFO_Empty: in std_logic; -- 1 port from Addr FIFO
		
		--2 ports to addr fifo
		Address_Output: out std_logic_vector(7 downto 0);
		Address_wrreq: out std_logic;
		
		--1 port to wenzhong
		Address_InputPortNumber: out std_logic_vector(1 downto 0);
		
		--1 port from length fifo		
		Length_FIFO_Full:in std_logic; --1 port from Length FIFO		
		
		--2 ports to length fifo
		Length_FIFO_output:out std_logic_vector(10 downto 0); --2 ports to Length FIFO
		Length_FIFO_wrreq:out std_logic
	);
	end component;
	

begin
	rcv_interface : SF_rcv_interface PORT MAP(
		reset			=>	reset,
		clk				=>	 clk,
		rcv_drdreq		=>	 rcv_drdreq,
		rcv_lrdreq		=>	 rcv_lrdreq,
		packet_finished		=>	 packet_finished,
		rcv0_data		=>	 rcv0_data,
		rcv1_data		=>	 rcv1_data,
		rcv2_data		=>	 rcv2_data,
		rcv3_data		=>	 rcv3_data,
		rcv0_length		=>	 rcv0_length,
		rcv1_length		=>	 rcv1_length,
		rcv2_length		=>	 rcv2_length, 
		rcv3_length		=>	 rcv3_length,
		rcv0_qempty		=>	 rcv0_qempty,
		rcv1_qempty		=>	 rcv1_qempty,
		rcv2_qempty		=>	 rcv2_qempty,
		rcv3_qempty		=>	 rcv3_qempty,
		rcv_data		=>	 rcv_data,
		rcv_length		=>	 rcv_length,
		port_number		=>	 rcv_port_number_from_rcv,
		connection_ready		=>	 rcv_connection_ready,
		rcv0_drdreq		=>	 rcv0_drdreq,
		rcv1_drdreq		=>	 rcv1_drdreq,
		rcv2_drdreq		=>	 rcv2_drdreq,
		rcv3_drdreq		=>	 rcv3_drdreq,
		rcv0_lrdreq		=>	 rcv0_lrdreq,
		rcv1_lrdreq		=>	 rcv1_lrdreq,
		rcv2_lrdreq		=>	 rcv2_lrdreq,
		rcv3_lrdreq		=>	 rcv3_lrdreq
	);	

	
	rec_handle : RecHandle PORT MAP(
		clk 			=>	clk,
		reset			=>	reset,
		
		Data_Read		=>	rcv_drdreq,  --4 ports out to RcvPortCycle  	
		Length_Read 	=> 	rcv_lrdreq,										
		Packet_Finished =>	packet_finished,
--		Packet_Error 	=> 	open,
		
		Data				=> rcv_data,  --5 ports in from RcvPortCycle   		
		Packet_Length 		=> rcv_length, --include valid						
		Connection_Ready	=> rcv_connection_ready,
--		Check_Counter		=> open,             --So, so far we do not need to implement this? If that is the case, I need to change my ending packet schedule.
		Input_Port_Number 	=> rcv_port_number_from_rcv,
		
		
		--internal SF FIFO control and input signals

		--1 port in from data FIFO
		FIFO_Full			=>dfifo_full,  --added for monitoring the data FIFO
		
		--2 ports to data FIFO
		Data_Output			=>dfifo_input,
		Data_wrreq			=>dfifo_wreq,
		
		--1 port from addr fifo		
		Address_FIFO_Empty	=>afifo_empty,
		
		--2 ports to addr fifo
		Address_Output		=>afifo_input, --changed from afifo_output because this should be the write port (BEF 3-28-09)
		Address_wrreq		=>afifo_wreq,
		
		--1 port to wenzhong
		Address_InputPortNumber =>rcv_port_number_to_xmt, -----------------------------needs work
		
		--1 port from length fifo		
		Length_FIFO_Full	=>lfifo_full,		
		
		--2 ports to length fifo
		Length_FIFO_output	=>lfifo_input(10 downto 0),
		Length_FIFO_wrreq	=>lfifo_wreq

	);
	
	lfifo_input(11) <= '0'; -- must set top bit to 0 by convention

end arch;